The present invention relates to a design technique for digital circuits. In particular, the present invention relates to a technique for speeding up signal transmission and a technique for reducing power consumption of the circuits.
In the current multimedia era, there is a demand for higher speed operational performance in fixed equipment, and lower power consumption in portable equipment. With these trends, a demand for high speed and low power consumption of semiconductor integrated circuits has become increasingly strong. On the other hand, under the promotion of miniaturization in the semiconductor process and multilayering of wiring, parasitic devices in wiring significantly affect the design. For example, an increase of the wiring resistance value and the wiring inductance value due to a reduction of the thickness of films for metal wiring and an increase of the wiring capacitance value due to a reduction of wiring pitch tend to prevent the achievement of high speed semiconductor integrated circuits and low power consumption.
Japanese Laid-Open Patent Publication No. 2-285711 discloses a signal transmission circuit for transmitting digital signals. In this signal transmission circuit, in order to realize high-speed driving of the signal line having a large load capacity, the voltage of a signal line is set to an intermediate voltage between a logic high voltage (Vdd) and a logic low voltage (Vss), and the signal line is driven to the logic high voltage or the logic low voltage by an inverter.
In this conventional signal transmission circuit, the voltage magnitude of the signal line (assuming Vss=0, the voltage magnitude is Vdd/2) is large. Therefore, it takes a long time to set the voltage of the signal lane to an intermediate voltage, and the power consumption become large.